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19-3348; Rev 0; 8/04
4A, 20ns, Dual MOSFET Drivers
General Description
The MAX5054-MAX5057 dual, high-speed MOSFET drivers source and sink up to 4A peak current. These devices feature a fast 20ns propagation delay and 20ns rise and fall times while driving a 5000pF capacitive load. Propagation delay time is minimized and matched between the inverting and noninverting inputs and between channels. High sourcing/sinking peak currents, low propagation delay, and thermally enhanced packages make the MAX5054-MAX5057 ideal for highfrequency and high-power circuits. The MAX5054-MAX5057 operate from a 4V to 15V single power supply and consume 40A (typ) of supply current when not switching. These devices have internal logic circuitry that prevents shoot-through during output state changes to minimize the operating current at high switching frequency. The logic inputs are protected against voltage spikes up to +18V, regardless of the VDD voltage. The MAX5054A is the only version that has CMOS input logic levels while the MAX5054B/MAX5055/ MAX5056/MAX5057 have TTL input logic levels. The MAX5055-MAX5057 provide the combination of dual inverting, dual noninverting, and inverting/noninverting input drivers. The MAX5054 feature both inverting and noninverting inputs per driver for greater flexibility. They are available in 8-pin TDFN (3mm x 3mm), standard SO, and thermally enhanced SO packages. These devices operate over the automotive temperature range of -40C to +125C. 4V to 15V Single Power Supply 4A Peak Source/Sink Drive Current 20ns (typ) Propagation Delay Matching Delay Between Inverting and Noninverting Inputs Matching Propagation Delay Between Two Channels VDD / 2 CMOS Logic Inputs (MAX5054AATA) TTL Logic Inputs (MAX5054B/MAX5055/MAX5056/MAX5057) 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input Hysteresis Up to +18V Logic Inputs (Regardless of VDD Voltage) Low Input Capacitance: 2.5pF (typ) 40A (typ) Quiescent Current -40C to +125C Operating Temperature Range 8-Pin TDFN and SO Packages
Features
MAX5054-MAX5057
Ordering Information
PART MAX5054AATA MAX5054BATA MAX5055AASA MAX5055BASA MAX5056AASA MAX5056BASA MAX5057AASA MAX5057BASA TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C PINPACKAGE 8 TDFN-EP* 8 TDFN-EP* 8 SO-EP* 8 SO 8 SO-EP* 8 SO 8 SO-EP* 8 SO TOP MARK AGS AGR -- -- -- -- -- --
Applications
Power MOSFET Switching Switch-Mode Power Supplies DC-DC Converters Motor Control Power-Supply Modules
Typical Operating Circuit
VIN VOUT
*EP = Exposed pad. Package code S8E-14. Selector Guide and Pin Configurations appear at end of data sheet.
MAX5054
VDD INA+ OUTA INA-
INB+ OUTB PWM IN INBGND
________________________________________________________________ Maxim Integrated Products
1
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.) VDD...............................................................................-0.3V to +18V INA+, INA-, INB+, INB- ...............................................-0.3V to +18V OUTA, OUTB...................................................-0.3V to (VDD + 0.3V) OUTA, OUTB Short-Circuit Duration ........................................10ms Continuous Source/Sink Current at OUT_ (PD < PDMAX) .....200mA Continuous Power Dissipation (TA = +70C) 8-Pin TDFN-EP (derate 24.4mW/C above +70C)........1951mW Junction-to-Case Thermal Resistance (JC) ......................2C/W 8-Pin SO-EP (derate 19.2mW/C above +70C)... ........1538mW Junction-to-Case Thermal Resistance (JC) ......................6C/W 8-Pin SO (derate 5.9mW/C above +70C)... ..................471mW Junction-to-Case Thermal Resistance (JC) ....................40C/W Operating Temperature Range..............................-40C to +125C Storage Temperature Range .................................-65C to +150C Junction Temperature ...........................................................+150C Lead Temperature (soldering, 10s)......................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER POWER SUPPLY VDD Operating Range VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis VDD Undervoltage Lockout to Output Delay IDD VDD Supply Current IDD-SW DRIVER OUTPUT (SINK) Driver Output Resistance Pulling Down Peak Output Current (Sinking) Output-Voltage Low Latchup Protection DRIVER OUTPUT (SOURCE) Driver Output Resistance Pulling Up Peak Output Current (Sourcing) VDD = 15V, IOUT_ = 100mA VDD = 4.5V, IOUT_ = 100mA TA = +25C TA = +125C TA = +25C TA = +125C 1.5 1.9 2.75 3.75 4 2.1 2.75 4 5.5 A ILUP VDD = 15V, IOUT_ = -100mA VDD = 4.5V, IOUT_ = -100mA TA = +25C TA = +125C TA = +25C TA = +125C VDD = 4.5V VDD = 15V 400 1.1 1.5 2.2 3.0 4 0.45 0.24 1.8 2.4 3.3 4.5 A V mA INA- = 0V, INB+ = VDD = 15V, INA+ = INB- both channels switching at 250kHz, CL = 0 1 2.4 4 mA VDD rising INA- = INB- = VDD, INA+ = INB+ = 0V (not switching) VDD = 4V VDD = 15V VDD UVLO VDD rising 4 3.00 3.50 200 12 28 40 55 A 75 15 3.85 V V mV s SYMBOL CONDITIONS MIN TYP MAX UNITS
RON-N
IPK-N
VDD = 15V, CL = 10,000pF IOUT_ = -100mA
Reverse current IOUT_ (Note 2)
RON-P
IPK-P
VDD = 15V, CL = 10,000pF
2
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4A, 20ns, Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS VDD = 4.5V Output-Voltage High IOUT_ = 100mA VDD = 15V LOGIC INPUT (Note 3) MAX5054A Logic 1 Input Voltage VIH MAX5054B/MAX5055/MAX5056/MAX5057 (Note 4) MAX5054A MAX5054B/MAX5055/MAX5056/MAX5057 Logic-Input Hysteresis Logic-Input-Current Leakage Input Capacitance CIN CL = 1000pF OUT_ Rise Time tR CL = 5000pF CL = 10,000pF CL = 1000pF OUT_ Fall Time Turn-On Delay Time Turn-Off Delay Time tF tD-ON tD-OFF CL = 5000pF CL = 10,000pF CL = 10,000pF (Note 2) CL = 10,000pF (Note 2) CL = 1000pF OUT_ Rise Time tR CL = 5000pF CL = 10,000pF CL = 1000pF OUT_ Fall Time Turn-On Delay Time Turn-Off Delay Time tF tD-ON tD-OFF CL = 5000pF CL = 10,000pF CL = 10,000pF (Note 2) CL = 10,000pF (Note 2) 18 18 10 10 VHYS MAX5054A MAX5054B/MAX5055/MAX5056/MAX5057 INA+, INB+, INA-, INB- = 0V or VDD -1 0.1 x VDD 0.3 +0.1 2.5 4 18 32 4 15 26 20 20 7 37 85 7 30 75 35 35 70 70 ns ns ns ns 34 34 ns ns ns ns +1 A pF 0.7 x VDD 2.1 0.3 x VDD 0.8 V MIN VDD 0.55 V VDD 0.275 TYP MAX UNITS
MAX5054-MAX5057
V
Logic 0 Input Voltage
VIL
V
SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1)
SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1)
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER MATCHING CHARACTERISTICS Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output Mismatch Propagation Delays Between Channel A and Channel B tON-OFF VDD = 15V, CL = 10,000pF VDD = 4.5V, CL = 10,000pF tA-B VDD = 15V, CL = 10,000pF VDD = 4.5V, CL = 10,000pF 2 ns 4 1 2 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4:
All devices are 100% tested at TA = +25C. Specifications over -40C to +125C are guaranteed by design. Limits are guaranteed by design, not production tested. The logic-input thresholds are tested at VDD = 4V and VDD = 15V. TTL compatible with reduced noise immunity.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
PROPAGATION DELAY TIME, LOW-TO-HIGH vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5054 toc02
RISE TIME vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5054 toc01
FALL TIME vs. SUPPLY VOLTAGE (CL = 5000pF)
60 50 TA = +125C FALL TIME (ns) 40 30 20 10 TA = +25C 60 50 PROPAGATION DELAY (ns) 40
50 TA = +125C RISE TIME (ns) 40 30 20 10 TA = -40C 0 4 6 8 10 12 14 TA = +25C
TA = +125C
TA = +25C 30 20 10 TA = -40C
TA = -40C 0 16 4 6 8 10 12 14 16 0 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PROPAGATION DELAY TIME, HIGH-TO-LOW vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5054 toc04
IDD-SW SUPPLY CURRENT vs. SUPPLY VOLTAGE
DUTY CYCLE = 50% VDD = 15V, CL = 0 1 CHANNEL SWITCHING
MAX5054 toc05
SUPPLY CURRENT vs. SUPPLY VOLTAGE
90 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 100kHz 50kHz 1MHz 500kHz DUTY CYCLE = 50% VDD = 15V, CL = 4700pF 1 CHANNEL SWITCHING
MAX5054 toc06
60 50 PROPAGATION DELAY (ns) 40 30 20 10 0 4 6 8 10 12 14 TA = -40C TA = +25C TA = +125C
6 IDD-SW SUPPLY CURRENT (mA) 5 4 3 2 1 0
100
1MHz 500kHz
100kHz
50kHz
0 4 6 8 10 12 14 16 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
16
SUPPLY VOLTAGE (V)
4
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MAX5054 toc03
60
4A, 20ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
IDD-SW SUPPLY CURRENT vs. TEMPERATURE
MAX5054 toc07
MAX5054-MAX5057
INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
MAX5054 toc08
INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
TTL INPUT VERSIONS
MAX5054 toc09
4.0 3.5 SUPPLY CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 -50 -25 0 25 50 75 100 VDD = 15V, f = 250kHz, CL = 0 DUTY CYCLE = 50% BOTH CHANNELS SWITCHING
10 9 INPUT THRESHOLD VOLTAGE (V) 8 7 6 5 4 3 2 1 0 VIN FALLING VIN RISING MAX5054AATA (CMOS INPUT)
3.0 INPUT THRESHOLD VOLTAGE (V) 2.5 2.0 1.5 1.0
VIN RISING
VIN FALLING 0.5 0
125
4
6
8
10
12
14
16
4
6
8
10
12
14
16
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH)
MAX5054 toc10
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW)
MAX5054 toc11
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH)
MAX5054AATA (CMOS INPUT) VDD = 15V 4 SUPPLY CURRENT (mA)
MAX5054 toc12
500 TTL INPUT VERSIONS VDD = 15V 400 SUPPLY CURRENT (A)
500 TTL INPUT VERSIONS VDD = 15V 400 SUPPLY CURRENT (A)
5
300
300
3
200
200
2
100
100
1
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW)
MAX5054 toc13
DELAY MISMATCH BETWEEN IN_+ AND IN_- TO OUT_ vs. TEMPERATURE
MAX5054 toc14
DELAY MISMATCH BETWEEN IN_+ AND IN_- TO OUT_ vs. TEMPERATURE
MAX5054 toc15
5 MAX5054AATA (CMOS INPUT) VDD = +15V 4 SUPPLY CURRENT (mA)
6 OUTPUT FALLING 4 DELAY MISMATCH (ns) 2 0 -2 -4 -6 OUTPUT RISING
6 4 DELAY MISMATCH (ns) 2 0 -2 -4 -6 OUTPUT FALLING OUTPUT RISING
3
2
1
MAX5054AATA (CMOS INPUT) VDD = 4.5V, CL = 10,000pF -50 -25 0 25 50 75 100 125
MAX5054AATA (CMOS INPUT) VDD = 15V, CL = 10,000pF -50 -25 0 25 50 75 100 125
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
DELAY MISMATCH BETWEEN 2 CHANNELS vs. TEMPERATURE
MAX5054 toc16
DELAY MISMATCH BETWEEN 2 CHANNELS vs. TEMPERATURE
VDD = 15V, CL = 10,000pF 3 DELAY MISMATCH (ns) 2 1 0 -1 -2 -3 -4 -50 -25 0 25 50 75 100 125 OUTPUT FALLING OUTPUT RISING
MAX5054 toc17
4 VDD = 4.5V, CL = 10,000pF 3 DELAY MISMATCH (ns) 2 1 0 -1 -2 -3 -4 -50 -25 0 25 50 75 100 OUTPUT RISING OUTPUT FALLING
4
125
TEMPERATURE (C)
TEMPERATURE (C)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF)
MAX5054 toc18
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF)
MAX5054 toc19
IN_2V/div
IN_2V/div
OUT_ 2V/div
OUT_ 2V/div
MAX5055 (TTL INPUT) 20ns/div
MAX5055 (TTL INPUT) 40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF)
MAX5054 toc20
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF)
MAX5054 toc21
IN_2V/div
IN_2V/div
OUT_ 2V/div OUT_ 2V/div MAX5055 (TTL INPUT) 20ns/div MAX5055 (TTL INPUT) 40ns/div
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4A, 20ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX5054-MAX5057
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF)
MAX5054 toc22
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF)
MAX5054 toc23
IN_2V/div
IN_2V/div
OUT_ 5V/div
OUT_ 5V/div
MAX5055 20ns/div 40ns/div
MAX5055
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF)
MAX5054 toc24
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF)
MAX5054 toc25
IN_2V/div
IN_2V/div
OUT_ 5V/div
OUT_ 5V/div
MAX5055 20ns/div 40ns/div
MAX5055
VDD vs. OUTPUT VOLTAGE
MAX5054 toc26
VDD vs. OUTPUT VOLTAGE
VDD 5V/div OUTA 5V/div OUTB 5V/div
MAX5054 toc27
MAX5055 INA- = INB- = GND CLA = CLB = 10,000pF
VDD 5V/div OUTA 5V/div OUTB 5V/div 2ms/div
MAX5055 INA- = INB- = GND CLA = CLB = 10,000pF 2ms/div
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Pin Descriptions
MAX5054
PIN 1 2 3 4 5 6 7 8 -- NAME INAINBGND OUTB VDD OUTA INB+ INA+ EP FUNCTION Inverting Logic-Input Terminal for Driver A. Connect to GND when not used. Inverting Logic-Input Terminal for Driver B. Connect to GND when not used. Ground Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off. Power Supply. Bypass to GND with one or more 0.1F ceramic capacitors. Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off. Noninverting Logic-Input Terminal for Driver B. Connect to VDD when not used. Noninverting Logic-Input Terminal for Driver A. Connect to VDD when not used. Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection.
MAX5055/MAX5056/MAX5057
PIN MAX5055 1, 8 2 3 4 5 6 7 -- -- -- MAX5056 1, 8 -- 3 -- 5 6 7 4 2 -- MAX5057 1, 8 2 3 -- 5 6 7 4 -- -- NAME N.C. INAGND INBOUTB VDD OUTA INB+ INA+ EP FUNCTION No Connection. Not internally connected. Inverting Logic-Input Terminal for Driver A. Connect to GND if not used. Ground Inverting Logic-Input Terminal for Driver B. Connect to GND if not used. Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off. Power Supply. Bypass to GND with one or more 0.1F ceramic capacitors. Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off. Noninverting Logic-Input Terminal for Driver B. Connect to VDD if not used. Noninverting Logic-Input Terminal for Driver A. Connect to VDD if not used. Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection.
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
VIH VIL
IN_+
VDD
90% OUT_ 10% tD-OFF1 tF IN_VIH VIL tD-OFF2 RISING MISMATCH = tD-ON2 - tD-ON1 FALLING MISMATCH = tD-OFF2 - tD-OFF1 tD-ON2 tD-ON1 tR
MAX5055 MAX5056 MAX5057
IN_+ BREAKBEFOREMAKE CONTROL
P OUT_ N
GND
Figure 1. Timing Diagram
NONINVERTING INPUT DRIVER
VDD VDD
MAX5054
IN_BREAKBEFOREMAKE CONTROL IN_+ N P OUT_ IN_-
MAX5055 MAX5056 MAX5057
BREAKBEFOREMAKE CONTROL
P OUT_ N
GND GND INVERTING INPUT DRIVER
Figure 2. MAX5054 Block Diagram (1 Driver)
Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams (1 Driver)
Detailed Description
VDD Undervoltage Lockout (UVLO)
The MAX5054-MAX5057 have internal undervoltage lockout for VDD. When VDD is below the UVLO threshold, OUT_ is low, independent of the state of the inputs. The undervoltage lockout is typically 3.5V with 200mV typical hysteresis to avoid chattering. When VDD rises above the UVLO threshold, the outputs go high or low depending upon the logic-input levels. Bypass VDD using low-ESR ceramic capacitors for proper operation (see the Applications Information section).
Logic Inputs
The MAX5054B-MAX5057 have TTL-compatible logic inputs, while the MAX5054A is a CMOS logic-input driver. The logic-input signals can be independent of the VDD voltage. For example, the device can be powered by a 5V supply while the logic inputs are provided from CMOS logic. Also, the logic inputs are protected against the voltage spikes up to 18V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 300mV and 0.1 x VDD hysteresis, respectively, to avoid possible double pulsing during transition. The low 2.5pF input capacitance reduces loading and increases switching speed.
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4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Table 1. MAX5054 Truth Table
INA+/INB+ Low Low High High INA-/INBLow High Low High OUTA/OUTB Low Low High Low
OFF ON INAGND PWM INPUT VDD
MAX5054A
INA+ OUTA
Table 2. MAX5055/MAX5056/MAX5057 Truth Table
NONINVERTING IN_+ Low High INVERTING IN_Low High OUT_ High Low OUT_ Low High
Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A)
Applications Information
RLC Series Circuit
The driver's RDS(ON) (RON), internal bond and lead inductance (LP), trace inductance (LS), gate inductance (LG), and gate capacitance (CG) form a series RLC circuit with a second-order characteristic equation. The series RLC circuit has an undamped natural frequency (0) and a damping ratio () where: 0 = 1 (LP + LS + LG ) x CG RON 2x (LP + LS + LG ) CG
The logic inputs are high impedance and must not be left floating. If the inputs are left open, OUT_ can go to an undefined state as soon as VDD rises above the UVLO threshold. Therefore, the PWM output from the controller must assume proper state when powering up the device. The MAX5054 has two logic inputs per driver providing greater flexibility in controlling the MOSFET. Use IN_+ for noninverting logic and IN_- for inverting logic operation. Connect IN_+ to V DD and IN_- to GND if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN_+ for active-low shutdown logic and IN_- for active-high shutdown logic (see Figure 4). See Table 1 for all possible input combinations.
=
Driver Output
The MAX5054-MAX5057 have low RDS(ON) p-channel and n-channel devices (totem pole) in the output stage for the fast turn-on and turn-off high gate-charge switching MOSFETs. The peak source or sink current is typically 4A. The OUT_ voltage is approximately equal to VDD when in high state and is ground when in low state. The driver R DS(ON) is lower at higher V DD , thus higher source-/sink-current capability and faster switching speeds. The propagation delays from the noninverting and inverting logic inputs to outputs are matched to 2ns. The break-before-make logic avoids any cross-conduction between the internal p- and n-channel devices, and eliminates shoot-through currents reducing the quiescent supply current.
The damping ratio needs to be greater than 0.5 (ideally 1) to avoid ringing. Add a small resistor (RGATE) in series with the gate when driving a very low gate-charge MOSFET, or when the driver is placed away from the MOSFET. Use the following equation to calculate the series resistor: (LP + LS + LG ) - RON CG
RGATE
LP can be approximated as 3nH and 2nH for SO and TDFN packages, respectively. LS is on the order of 20nH/in. Verify LG with the MOSFET vendor.
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4A, 20ns, Dual MOSFET Drivers
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the MAX5054-MAX5057. Peak supply and output currents may exceed 8A when both drivers drive large external capacitive loads in phase. Supply voltage drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, OUT_, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5054-MAX5057 with any capacitive load. Place one or more 0.1F ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND. Use a ground plane to minimize ground return resistance and series inductance. Place the external MOSFET as close as possible to the MAX5054-MAX5057 to further minimize board inductance and AC path impedance. where D (duty cycle) is the fraction of the period the MAX5054-MAX5057's output pulls high duty cycle, RON(MAX) is the maximum on-resistance of the device with the output high, and ILOAD is the output load current of the MAX5054-MAX5057.
MAX5054-MAX5057
Layout Information
The MAX5054-MAX5057 MOSFET drivers source and sink large currents to create very fast rising and falling edges at the gate of the switching MOSFET. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5054-MAX5057: * Place one or more 0.1F decoupling ceramic capacitors from VDD to GND as close to the device as possible. Connect VDD and GND to large copper areas. Place one bulk capacitor of 10F (min) on the PC board with a low resistance path to the VDD input and GND of the MAX5054-MAX5057. Two AC current loops form between the device and the gate of the driven MOSFET. The MOSFET looks like a large capacitance from gate to source when the gate pulls low. The active current loop is from the MOSFET gate to OUT_ of the MAX5054-MAX5057, to GND of the MAX5054-MAX5057, and to the source of the MOSFET. When the gate of the MOSFET pulls high, the active current is from the VDD terminal of the decoupling capacitor, to V DD of the MAX5054- MAX5057, to OUT_ of the MAX5054-MAX5057, to the MOSFET gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. Keep the device as close to the MOSFET as possible. In a multilayer PC board, the inner layers should consist of a GND plane containing the discharging and charging current loops. Pay extra attention to the ground loop and use a low-impedance source when using a TTL logicinput device. Fast fall time at OUT_ may corrupt the input during transition.
Power Dissipation
Power dissipation of the MAX5054-MAX5057 consists of three components: caused by the quiescent current, capacitive charge/discharge of internal nodes, and the output current (either capacitive or resistive load). Maintain the sum of these components below the maximum power dissipation limit. The current required to charge and discharge the internal nodes is frequency dependent (see the Supply Current vs. Supply Voltage graph in the Typical Operating Characteristics). The power dissipation (PQ) due to the quiescent switching supply current (IDD-SW) per driver can be calculated as: PQ = VDD x IDD-SW For capacitive loads, use the following equation to estimate the power dissipation per driver: PCLOAD = CLOAD x (VDD)2 x fSW where CLOAD is the capacitive load, VDD is the supply voltage, and fSW is the switching frequency. Calculate the total power dissipation (PT) per driver as follows: PT = PQ + PCLOAD Use the following equation to estimate the MAX5054- MAX5057 total power dissipation per driver when driving a ground-referenced resistive load: PT = PQ + PRLOAD PRLOAD = D x RON(MAX) x ILOAD2
*
* *
*
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11
4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Exposed Pad
Both the SO-EP and TDFN-EP packages have an exposed pad on the bottom of their package. These pads are internally connected to GND. For the best thermal conductivity, solder the exposed pad to the ground plane to dissipate 1.5W and 1.9W in SO-EP and TDFN-EP packages, respectively. Do not use the ground-connected pads as the only electrical ground connection or ground return. Use GND (pin 3) as the primary electrical ground connection.
Additional Application Circuits
VOUT
VIN
MAX5054
VDD INA+ OUTA INA-
MAX5054
VDD PWM IN INA+ OUTA INA-
VDD INB+ OUTB PWM IN INBGND
PWM IN
INB+ OUTB INBGND
Figure 5. Push-Pull Converter with Synchronous Rectification Drive Using MAX5054
12
______________________________________________________________________________________
REG5 XFRMRH +VIN 2 +VIN XFRMRH 1 R29 1 DRVB -VIN 1 4 5V 1 IN U5 EN N.C. 6 HOLD 5 VOUT VOUT C14 270F 4V C15 270F 4V C33 1F 10V WDI 7 2 C16 3.3F OUT REG9 2 2 C32 1F 3 GND 4 21 20 XFRMRH XFRMRH 2 T1 N4 14 8 +VIN 8T 5 2 65 8 2T 10 1 87 OUTA U4 N3 3 2 1 4 +VIN +5V 7 C21 4.7F 80V 1 INB+ VDD 5 C30 0.1F INAGND 3 4 OUTB D7 2 R18 4.7 PVIN R22 15k 6 5 6 C23 1000pF 8 INA+ C31 5V 0.1F 5 4 VCC U6 OUT INB2 3 +5V GND CA 2 AN 1 2 D5 6 1 4T 1 4 1 2 C20 220pF R14 270 R17 0.027 1% 3 7 N2 C9 1F D3 1 R9 8.2 C34 330pF 1 87 D4 R10 2 3 20 2 C13 270F 4V 56 DRVB REG9 DRVDD PGND 17 18 19 R8 8.2 R13 47 RESET L1 2.4H 1 D6 D1 2 C8 4.7F R7 0 8 N5 3 C35 1F 5 6 R5 38.3k 1% C10 0.47F 100V C11 0.47F 100V C12 1F 100V C25 0.047F 100V D2 1 3 2 N1 8 7 +VIN 1 RCOSC U1 SYNCIN 28 R4 1M 1% C7 0.22F R6 1M 1%
R21 24.9k 1%
C1 100pF
MAX5051
FLTINT 2 SYNCOUT RCFF UVLO GND 4 COM 5 CSS AVIN BST DRVH 7 FB DRVB REG5 REG9 PVIN STT LXVDD IC_PADDLE LXH VOUT R20 0 R19 475 R12 100k 1% VOUT 3 OUT FB TRIM 5 R2 2.55k 1% C36 C28 R1 0.22F 0.047F 11.5k 1% VOUT R23 10 SENSE (+) SENSE (-) U3 C27 0.15F LXL 29 16 DRVL 15 CS 8 9 10 11 12 XFRMRH 22 23 6 COMP 24 +VIN 25 STARTUP 26 ON/OFF 3 27
+VIN
R25 100k
TP1
C2 390pF
2
D8
1
C5 4700pF
R16 10.5k 1%
R15 31.6k 1%
C4 4.7F
REG5
REG9
C3 4.7F
SGND
C6 0.1F
PVIN
LXH R26 560
REG5
C18 1000pF
R27 10 13 14
C19 1F
MAX5054
R28 2k
LXH
TP3
REG5
R3 2.2k U2 1
4
Figure 6. Schematic of a 48V Input, 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply
2 C22 2200pF 2kV REG9 4 IN 1 PGND 2 GND C26 0.1F R24 10 U1: MAX5051 U2: PS2913-1-M U3: MAX8515 U4: MAX5054 U5: MAX5023M U6: PS9715 N1, N2: SI4486 N3, N4: SI4864 N5: BSS123
C24 1000pF
R11 360
3
MAX5054-MAX5057
______________________________________________________________________________________
C17 0.33F
4A, 20ns, Dual MOSFET Drivers
13
4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Pin Configurations
TOP VIEW MAX5054
INAINBGND 1 2 3 8 7 6 5 INA+ INB+ OUTA VDD N.C. 1
MAX5055
8 7 6 5 N.C. OUTA VDD OUTB
INA- 2 GND 3
OUTB 4
INB- 4
TDFN-EP MAX5056
N.C. INA+ GND 1 2 3 8 7 6 5 N.C. OUTA VDD OUTB N.C. 1
SO/SO-EP MAX5057
8 7 6 5 N.C. OUTA VDD OUTB
INA- 2 GND 3
INB+ 4
INB+ 4
SO/SO-EP
SO/SO-EP
Selector Guide
PART MAX5054AATA MAX5054BATA MAX5055AASA MAX5055BASA MAX5056AASA MAX5056BASA MAX5057AASA MAX5057BASA PINPACKAGE 8 TDFN-EP* 8 TDFN-EP* 8 SO-EP* 8 SO 8 SO-EP* 8 SO 8 SO-EP* 8 SO LOGIC INPUT VDD / 2 CMOS Dual Inverting and Dual Noninverting Inputs TTL Dual Inverting and Dual Noninverting Inputs TTL Dual Inverting Inputs TTL Dual Inverting Inputs TTL Dual Noninverting Inputs TTL Dual Noninverting Inputs TTL Inverting and Noninverting Inputs TTL Inverting and Noninverting Inputs
Chip Information
TRANSISTOR COUNT: 258 PROCESS: CMOS
*EP = Exposed pad.
14
______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5054-MAX5057
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D A e B A1 L C
0-8
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
______________________________________________________________________________________
SOICN .EPS
15
4A, 20ns, Dual MOSFET Drivers MAX5054-MAX5057
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
8L, SOIC EXP. PAD.EPS
PACKAGE OUTLINE 8L SOIC, .150" EXPOSED PAD
21-0111
B
1
1
16
______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX5054-MAX5057
D
N
PIN 1 INDEX AREA
E
DETAIL A
E2
C L
C L
L A e e
L
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
21-0137
F
1
2
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 MAX. 0.80 3.10 3.10 0.05
0.40 0.20 0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 T1433-1 T1433-2 N 6 8 10 14 14 D2 1.500.10 1.500.10 1.500.10 1.700.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 ------b 0.400.05 0.300.05 0.250.05 0.200.03 0.200.03 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF 2.40 REF 2.40 REF
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
F
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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